Synthesis of Controllers from Interval Temporal Logic Specification

ed state machines Deterministic state machines 1. State machine extraction (e.g. stg_extract) 2. Eliminate conditions New constraints in ITL 3. Sequential circuits 5. Logic synthesis 4. Sythesizer (tableau and determinize) KISS2 interface Figure 2: Flow of Our Redesign Method 4 A Redesign Method We cannot handle very complex ITL formulas within a reasonable time, since the expansion time grows exponentially with the number of temporal operators in the worst case. So, more practical situation is to use ITL formulas as a partial specification for the system being designed. This redesign method for sequential circuits are shown in Figure 2. The (possibly non-deterministic) state machines can be obtained from existing sequential circuits. First we extract state machines from given sequential circuits by the procedure such as stg extract in SIS (1. in Figure 2). Then the conditions for variables which must be modified are eliminated from the generated state machines. This process generates possibly non-deterministic state machines in the sense that the eliminated constraints for variables are not sensed and controlled (2. in Figure 2). Then we provide ITL formulas for the specification of the eliminated variables so that they satisfy the required properties. (3. in Figure 2). By using deterministic tableau methods on the ITL formulas and the existing sequential circuits, the resulting state machine is the one we wanted, i.e., the one which satisfies both the properties in the extracted state machine and the ones in ITL formulas (4. in Figure 2). The final state machine can be logic synthesized and the desired sequential circuit is obtained (5. in Figure 2). If we want a sequential circuit which satisfy the new